Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs

Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems

Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs

This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the ...

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era

0740-7475/02/$17.00 © 2002 IEEE September–October 2002 CMOS IC SCALING increases device/interconnect density to allow more logic on a die at higher clock rates, enhancing overall performance. Improvements in process technology enable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to marke...

In This Issue Editorial 1 Introduction to the Special Issue 2

And now for some thing completely different-a " Spanish " Informer. That's right – this edition is a one-off special, focusing exclusively on the IR scene in Spain. There's a great mix of articles, covering both the latest developments from the academic community and a review of one of the newest and most influential commercial research organisations – Yahoo's Barcelona labs. All this has been ...

Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters

In this paper, we present a complete design methodology for high-performance low-power Analog-to-Digital Converters in deep submicron CMOS. This methodology is demonstrated on two ADC architectures, Flash and Folding&Interpolating(F&I). The designs were implemented in 0.18μm CMOS technology, achieving a high conversion rate of 2.6 GSamples/s for the Flash converter, and a 1 GSample/s rate for t...